Datasheet

Processor Configuration Registers
198 Datasheet, Volume 2
2.15.8 FSTS_REG—Fault Status Register
This register indicates the primary fault logging status. The VTd specification describes
hardware behavior for primary fault logging.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 34–37h
Reset Value: 00000000h
Access: RO, RO-V-S, RW1C-S
Bit Attr
Reset
Value
Description
31:16 RO 0000h Reserved
15:8 RO-V-S 00h
Fault Record Index (FRI)
This field is valid only when the PPF field is set. The FRI field indicates the index
(from base) of the fault recording register to which the first pending fault was
recorded when the PPF field was set by hardware.
Valid values for this field are from 0 to N, where N is the value reported through
NFR field in the Capability register. The value read from this field is undefined
when the PPF field is clear.
7RO0bReserved
6RW1C-S0b
Invalidation Time-out Error (ITE)
Hardware detected a Device-IOTLB invalidation completion time-out. At this time,
a fault event may be generated based on the programming of the Fault Event
Control register. Hardware implementations not supporting Device-IOTLBs
implement this bit as reserved.
5RW1C-S0b
Invalidation Completion Error (ICE)
Hardware received an unexpected or invalid Device-IOTLB invalidation completion.
This could be due to either an invalid ITag or invalid source-id in an invalidation
completion response. At this time, a fault event may be generated based on the
programming of the Fault Event Control register. Hardware implementations not
supporting Device-IOTLBs implement this bit as reserved.
4RW1C-S0b
Invalidation Queue Error (IQE)
Hardware detected an error associated with the invalidation queue. This could be
due to either a hardware error while fetching a descriptor from the invalidation
queue, or hardware detecting an erroneous or invalid descriptor in the invalidation
queue. At this time, a fault event may be generated based on the programming of
the Fault Event Control register. Hardware implementations not supporting queued
invalidations implement this bit as reserved.
3RW1C-S0b
Advanced Pending Fault (APF)
When this field is Clear, hardware sets this field when the first fault record (at
index 0) is written to a fault log. At this time, a fault event is generated based on
the programming of the Fault Event Control register. Software writing 1 to this
field clears it. Hardware implementations not supporting advanced fault logging
implement this bit as reserved.
2RW1C-S0b
Advanced Fault Overflow (AFO)
Hardware sets this field to indicate advanced fault log overflow condition. At this
time, a fault event is generated based on the programming of the Fault Event
Control register. Software writing 1 to this field clears it. Hardware
implementations not supporting advanced fault logging implement this bit as
reserved.
1RO-V-S0h
Primary Pending Fault (PPF)
This field indicates if there are one or more pending faults logged in the fault
recording registers. Hardware computes this field as the logical OR of Fault (F)
fields across all the fault recording registers of this DMA-remapping hardware unit.
0 = No pending faults in any of the fault recording registers
1 = One or more fault recording registers has pending faults. The FRI field is
updated by hardware whenever the PPF field is set by hardware. Also,
depending on the programming of the Fault Event Control register, a fault
event is generated when hardware sets this field.
0RW1C-S0h
Primary Fault Overflow (PFO)
Hardware sets this field to indicate overflow of fault recording registers. Software
writing 1 clears this field.