Datasheet

Datasheet, Volume 2 191
Processor Configuration Registers
2.15.4 GCMD_REG—Global Command Register
This register controls DMA-remapping hardware. If multiple control fields in this
register need to be modified, software must serialize through multiple writes to this
register.
2RO 0b
Device IOTLB Support (DI)
0 = Hardware does not support device- IOTLBs.
1 = Hardware supports Device-IOTLBs. Implementations reporting this field
as Set must also support Queued Invalidation (QI = 1b).
1RO 0b
Queued Invalidation Support (QI)
0 = Hardware does not support queued invalidations.
1 = Hardware supports queued invalidations.
0RO 0b
Coherency (C)
0 = Indicates that hardware accesses to the root, context, and page table
structures are non-coherent (non-snoop).
1 = Indicates that hardware accesses to the root, context, and page table
structures are coherent (snoop).
Hardware writes to the advanced fault log is required to be coherent
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 10–17h
Reset Value: 0000000000001000h
Access: RO
Bit Attr
Reset
Value
Description
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 18–1Bh
Reset Value: 00000000h
Access: W, WO, RO
Bit Attr
Reset
Value
Description
31 W 0b
Translation Enable (TE)
Software writes to this field to request hardware to enable/disable DMA-
remapping hardware.
0 = Disable DMA-remapping hardware
1 = Enable DMA-remapping hardware
Hardware reports the status of the translation enable operation through the
TES field in the Global Status register.
Before enabling (or re-enabling) DMA-remapping hardware through this field,
software must:
Setup the DMA-remapping structures in memory
Flush the write buffers (through WBF field), if write buffer flushing is
reported as required.
Set the root-entry table pointer in hardware (through SRTP field).
Perform global invalidation of the context-cache and global invalidation of
IOTLB
If advanced fault logging supported, setup fault log pointer (through SFL
field) and enable advanced fault logging (through EAFL field).
Refer to the VTd specification for detailed software requirements.
There may be active DMA requests in the platform when software updates this
field. Hardware must enable or disable remapping logic only at deterministic
transaction boundaries, so that any in-flight transaction is either subject to
remapping or not at all.
Hardware implementations supporting DMA draining must drain any in-flight
translated DMA read/write requests queued within the root complex before
completing the translation enable command and reflecting the status of the
command through the TES field in the GSTS_REG.
Value returned on read of this field is undefined.