Datasheet

Datasheet, Volume 2 189
Processor Configuration Registers
6RO 1b
Protected High-Memory Region (PHMR)
0 = Indicates protected high-memory region not supported.
1 = Indicates protected high-memory region is supported.
DMA-remapping hardware implementations on Intel TXT platforms
supporting main memory above 4 GB are required to support protected high-
memory region.
5RO 1b
Protected Low-Memory Region (PLMR)
0 = Indicates protected low-memory region not supported.
1 = Indicates protected low-memory region is supported.
DMA-remapping hardware implementations on Intel TXT platforms are
required to support protected low-memory region.
4RO 1b
Required Write-Buffer Flushing (RWBF)
0 = Indicates no write-buffer flushing needed to ensure changes to memory-
resident structures are visible to hardware.
1 = Indicates software must explicitly flush the write buffers (through the
Global Command register) to ensure updates made to memory-resident
DMA-remapping structures are visible to hardware.
Refer to the VTd specification for more details on write buffer flushing
requirements.
3RO 0b
Advanced Fault Logging (AFL)
0 = Indicates advanced fault logging not supported. Only primary fault
logging is supported.
1 = Indicates advanced fault logging is supported.
2:0 RO 010b
Number of domains supported (ND)
000b = Hardware supports 4-bit domain-ids with support for up to 16
domains.
001b =Hardware supports 6-bit domain-ids with support for up to 64
domains.
010b = Hardware supports 8-bit domain-ids with support for up to 256
domains.
011b = Hardware supports 10-bit domain-ids with support for up to 1024
domains.
100b = Hardware supports 12-bit domain-ids with support for up to 4K
domains.
101b = Hardware supports 14-bit domain-ids with support for up to 16K
domains.
110b = Hardware supports 16-bit domain-ids with support for up to 64K
domains.
111b =Reserved.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 8–Fh
Reset Value: 00C9008020630272h
Access: RO
Bit Attr
Reset
Value
Description