Datasheet

Processor Configuration Registers
188 Datasheet, Volume 2
23 RO 0b
Isochrony (Isoch)
0 = Indicates this DMA-remapping hardware unit has no critical isochronous
requesters in its scope.
1 = Indicates this DMA-remapping hardware unit has one or more critical
isochronous requesters in its scope. To ensure isochronous performance,
software must ensure invalidation operations do not impact active DMA
streams. This implies that when DMA is active, software perform page-
selective invalidations (instead of coarser invalidations).
22 RO 1b
Zero Length Read (ZLR)
0 = Indicates the remapping hardware unit blocks (and treats as fault) zero
length DMA read requests to write-only pages.
1 = Indicates the remapping hardware unit supports zero length DMA read
requests to write-only pages.
21:16 RO 100011b
Maximum Guest Address Width (MGAW)
This field indicates the maximum DMA virtual addressability supported by
remapping hardware.
The Maximum Guest Address Width (MGAW) is computed as (N+1), where N
is the value reported in this field.
For example, a hardware implementation supporting 48-bit MGAW reports a
value of 47 (101111b) in this field.
If the value in this field is X, DMA requests to addresses above 2(x+1)–1 are
always blocked by hardware. Guest addressability for a given DMA request is
limited to the minimum of the value reported through this field and the
adjusted guest address width of the corresponding page-table structure.
(Adjusted guest address widths supported by hardware are reported through
the SAGAW field).
15:13 RO 000b Reserved
12:8 RO 00010b
Supported Adjusted Guest Address Widths (SAGAW)
This 5-bit field indicates the supported adjusted guest address widths (which
in turn represents the levels of page-table walks) supported by the hardware
implementation.
A value of 1 in any of these bits indicates the corresponding adjusted guest
address width is supported. The adjusted guest address widths
corresponding to various bit positions within this field are:
0 = 30-bit AGAW (2-level page table)
1 = 39-bit AGAW (3-level page table)
2 = 48-bit AGAW (4-level page table)
3 = 57-bit AGAW (5-level page table)
4 = 64-bit AGAW (6-level page table)
Software must ensure that the adjusted guest address width used to setup
the page tables is one of the supported guest address widths reported in this
field.
7RO 0b
Caching Mode (CM)
0 = Hardware does not cache not present and erroneous entries in the
context-cache and IOTLB. Invalidations are not required for
modifications to individual not present or invalid entries. However, any
modifications that result in decreasing the effective permissions or
partial permission increases require invalidations for them to be
effective.
1 = Hardware may cache not present and erroneous mappings in the
context-cache or IOTLB. Any software updates to the DMA-remapping
structures (including updates to not-present or erroneous entries)
require explicit invalidation.
Refer to the VTd specification for more details on caching mode.
Hardware implementations are recommended to support operation
corresponding to CM=0.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 8–Fh
Reset Value: 00C9008020630272h
Access: RO
Bit Attr
Reset
Value
Description