Datasheet

Datasheet, Volume 2 187
Processor Configuration Registers
2.15.2 CAP_REG—Capability Register
This register reports general DMA remapping hardware capabilities.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 8–Fh
Reset Value: 00C9008020630272h
Access: RO
Bit Attr
Reset
Value
Description
63:56 RO 00h Reserved
55 RO 1b
DMA Read Draining (DRD)
0 = On IOTLB invalidations, hardware does not support draining of
translated DMA read requests queued within the root complex.
1 = On IOTLB invalidations, hardware supports draining of translated DMA
read requests queued within the root complex. Indicates supported
architecture version.
54 RO 1b
DMA Write Draining (DWD)
0 = On IOTLB invalidations, hardware does not support draining of
translated DMA writes queued within the root complex.
1 = On IOTLB invalidations, hardware supports draining of translated DMA
writes queued within the root complex.
53:48 RO 001001b
Maximum Address Mask Value (MAMV)
The value in this field indicates the maximum supported value for the
Address Mask (AM) field in the Invalidation Address (IVA_REG) register.
47:40 RO
00000000
b
Number of Fault Recording Registers (NFR)
This field indicates a value of N-1, where N is the number of fault recording
registers supported by hardware.
Implementations must support at least one fault recording register (NFR = 0)
for each DMA-remapping hardware unit in the platform. The maximum
number of fault recording registers per DMA-remapping hardware unit is 256.
Bit 40 in the capability register is the least significant bit of the NFR field
(47:40).
39 RO 1b
Page Selective Invalidation Support (PSI)
0 = DMAr engine does not support page selective invalidations
1 = DMAr engine does support page-selective IOTLB invalidations. The
MAMV field indicates the maximum number of contiguous translations
that may be invalidated in a single request.
38 RO 0b Reserved
37:34 RO 0000b
Super Page Support (SPS)
This field indicates the super page sizes supported by hardware. A value of 1
in any of these bits indicates the corresponding super-page size is supported.
The super-page sizes corresponding to various bit positions within this field
are:
0 = 21-bit offset to page frame
1 = 30-bit offset to page frame
2 = 39-bit offset to page frame
3 = 48-bit offset to page frame
33:24 RO 020h
Fault-recording Register offset (FRO)
This field specifies the location to the first fault recording register relative to
the register base address of this DMA-remapping hardware unit.
If the register base address is X, and the value reported in this field is Y, the
address for the first fault recording register is calculated as X+(16*Y).