Datasheet

Datasheet, Volume 2 181
Processor Configuration Registers
2.13.12 IOBAR—I/O Base Address Register
This register provides the Base offset of the I/O registers within Device 2. Bits 15:3 are
programmable allowing the I/O Base to be located anywhere in 16bit I/O Address
Space. Bits 2:1 are fixed and return zero, bit 0 is hardwired to a one indicating that 8
bytes of I/O space are decoded. Access to the 8Bs of IO space is allowed in PM state D0
when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1–D3 or if IO
Enable is clear or if Device 2 is turned off or if Internal graphics is disabled thru the fuse
or fuse override mechanisms.
Note that access to this IO BAR is independent of VGA functionality within Device 2.
Also note that this mechanism is available only through function 0 of Device 2 and is
not duplicated in function 1.
If accesses to this IO bar are allowed, the processor claims all 8, 16, or 32 bit IO cycles
from the processor that falls within the 8B claimed.
2.13.13 SVID2—Subsystem Vendor Identification Register
B/D/F/Type: 0/2/0/PCI
Address Offset: 20–23h
Reset Value: 0000_0001h
Access: RO, RW
Bit Attr
Reset
Value
Description
31:16 RO 0000h Reserved
15:3 RW 0000h
I/O Base Address (IOBASE)
This field is set by the OS. The bits correspond to address signals [15:3].
2:1 RO 00b
Memory Type (MEMTYPE)
Hardwired to 0s to indicate 32-bit address.
0RO 1b
Memory/IO Space (MIOS)
Hardwired to 1 to indicate I/O space.
B/D/F/Type: 0/2/0/PCI
Address Offset: 2C–2Dh
Reset Value: 0000h
Access: RW-O
Bit Attr
Reset
Value
Description
15:0 RW-O 0000h
Subsystem Vendor ID (SUBVID)
This value is used to identify the vendor of the subsystem. This register
should be programmed by BIOS during boot-up. Once written, this register
becomes Read Only. This register can only be cleared by a Reset.