Datasheet

Datasheet, Volume 2 179
Processor Configuration Registers
2.13.10 GTTMMADR—Graphics Translation Table, Memory Mapped
Range Address Register
This register requests allocation for the combined Graphics Translation Table
Modification Range and Memory Mapped Range. The range requires 4 MB combined for
MMIO and Global GTT aperture, with 512K of that used by MMIO and 2MB used by GTT.
GTTADR will begin at (GTTMMADR + 2 MB) while the MMIO base address will be the
same as GTTMMADR.
For the Global GTT, this range is defined as a memory BAR in graphics device config
space. It is an alias into which software is required to write Page Table Entry values
(PTEs). Software may read PTE values from the global Graphics Translation Table
(GTT). PTEs cannot be written directly into the global GTT memory area.
The device snoops writes to this region in order to invalidate any cached translations
within the various TLBs implemented on-chip.
The allocation is for 4 MB and the base address is defined by bits [35:22].
B/D/F/Type: 0/2/0/PCI
Address Offset: 10–17h
Reset Value: 0000_0000_0000_0004h
Access: RW, RO
Bit Attr
Reset
Value
Description
63:36 RW 0000000h
Reserved: Reserved for Memory Base Address
Must be set to 0 since addressing above 64 GB is not supported.
35:22 RW 0000h
Memory Base Address (MBA)
Set by the OS, these bits correspond to address signals [35:22]. 4 MB
combined for MMIO and Global GTT table aperture (512 KB for MMIO and
2MB for GTT).
21:4 RO 00000h
Reserved
Hardwired to 0s to indicate at least 4 MB address range.
3RO 0b
Prefetchable Memory (PREFMEM)
Hardwired to 0 to prevent prefetching.
2:1 RO 10b
Memory Type (MEMTYP)
00 = To indicate 32 bit base address
01 = Reserved
10 = To indicate 64 bit base address
11 = Reserved
0RO 0b
Memory/IO Space (MIOS)
Hardwired to 0 to indicate memory space.