Datasheet
Processor Configuration Registers
178 Datasheet, Volume 2
2.13.7 CLS—Cache Line Size Register
The IGD does not support this register as a PCI slave.
2.13.8 MLT2—Master Latency Timer Register
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
2.13.9 HDR2—Header Type Register
This register contains the Header Type of the IGD.
B/D/F/Type: 0/2/0/PCI
Address Offset: Ch
Reset Value: 00h
Access: RO
Bit Attr
Reset
Value
Description
7:0 RO 00h
Cache Line Size (CLS)
This field is hardwired to 0s. The IGD as a PCI compliant master does not use
the Memory Write and Invalidate command and, in general, does not perform
operations based on cache line size.
B/D/F/Type: 0/2/0/PCI
Address Offset: Dh
Reset Value: 00h
Access: RO
Bit Attr
Reset
Value
Description
7:0 RO 00h Master Latency Timer Count Value (MLTCV)
Hardwired to 0s.
B/D/F/Type: 0/2/0/PCI
Address Offset: Eh
Reset Value: 00h
Access: RO
Bit Attr
Reset
Value
Description
7RO 0b
Multi Function Status (MFUNC)
Indicates if the device is a Multi-Function Device. The value is hardwired to 0
to indicate that this Internal Graphics Device is a single-function device.
6:0 RO 00h
Header Code (H)
This is a 7-bit value that indicates the Header Code for the IGD. This code
has the value 00h, indicating a type 0 configuration space format.