Datasheet

Datasheet, Volume 2 175
Processor Configuration Registers
2.13.2 DID2—Device Identification Register
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
2.13.3 PCICMD2—PCI Command Register
This 16-bit register provides basic control over the IGD ability to respond to PCI cycles.
The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to
main memory.
B/D/F/Type: 0/2/0/PCI
Address Offset: 2–3h
Reset Value: 0042h
Access: RO
Bit Attr
Reset
Value
Description
15:0 RO 0042h
Device Identification Number (DID)
This is a 16 bit value assigned to the processor Graphics device.
B/D/F/Type: 0/2/0/PCI
Address Offset: 4–5h
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:11 RO 00h Reserved
10:10 RO 0h Reserved
9RO 0b
Fast Back-to-Back (FB2B)
Not Implemented. Hardwired to 0.
8RO 0b
SERR Enable (SERRE)
Not Implemented. Hardwired to 0.
7RO 0b
Address/Data Stepping Enable (ADSTEP)
Not Implemented. Hardwired to 0.
6RO 0b
Parity Error Enable (PERRE)
Not Implemented. Hardwired to 0. Since the IGD belongs to the category of
devices that does not corrupt programs or data in system memory or hard
drives, the IGD ignores any parity error that it detects and continues with
normal operation.
5RO 0b
Video Palette Snooping (VPS)
This bit is hardwired to 0 to disable snooping.
4RO 0b
Memory Write and Invalidate Enable (MWIE)
Hardwired to 0. The IGD does not support memory write and invalidate
commands.
3RO 0b
Special Cycle Enable (SCE)
This bit is hardwired to 0. The IGD ignores Special cycles.
2RW 0b
Bus Master Enable (BME)
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
1RW 0b
Memory Access Enable (MAE)
This bit controls the IGD response to memory space accesses.
0 = Disable
1 = Enable
0RW 0b
I/O Access Enable (IOAE)
This bit controls the IGD response to I/O space accesses.
0 = Disable
1 = Enable