Datasheet
Datasheet, Volume 2 173
Processor Configuration Registers
2.12.19 DMILCTL—DMI Link Control Register
This register allows control of DMI.
2.12.20 DMILSTS—DMI Link Status Register
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 88–89h
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:8 RO 00h Reserved
7RW 0b
Extended Synch (EXTSYNC)
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting the L0s
state and when in the Recovery state.
This mode provides external devices (such as, logic analyzers) monitoring
the Link time to achieve bit and symbol lock before the link enters L0 and
resumes communication.
This is a test mode only and may cause other undesired side effects such as
buffer overflows or underruns.
6:3 RO 0h Reserved
2RO 0bReserved
1:0 RW 00b
Active State Power Management Support (ASPMS)
This field controls the level of active state power management supported on
the given link.
00 = Disabled
01 = L0s Entry Supported
10 = L1 Entry Enabled
11 = L0s and L1 Entry Supported
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 8A–8Bh
Reset Value: 0001h
Access: RO
Bit Attr
Reset
Value
Description
15:10 RO 00h Reserved
9:4 RO 00h
Negotiated Width (NWID)
This field indicates negotiated link width. This field is valid only when the link
is in the L0, L0s, or L1 states (after link width negotiation is successfully
completed).
00h = Reserved
01h = X1
02h = X2
04h = X4
All other encodings are reserved.
3:0 RO 1h
Negotiated Speed (NSPD)
This field indicates negotiated link speed.
1h = 2.5 Gb/s
All other encodings are reserved.