Datasheet

Datasheet, Volume 2 171
Processor Configuration Registers
2.12.16 DMILE2D—DMI Link Entry 2 Description Register
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
2.12.17 DMILE2A—DMI Link Entry 2 Address Register
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 60–63h
Reset Value: 0000_0000h
Access: RO, RWO
Bit Attr
Reset
Value
Description
31:24 RO 00h
Target Port Number (TPN)
This field specifies the port number associated with the element targeted by
this link entry (Egress Port). The target port number is with respect to the
component that contains this element as specified by the target component
ID.
23:16 RW-O 00h
Target Component ID (TCID
This field identifies the physical or logical component that is targeted by this
link entry.
BIOS Requirement: Must be initialized according to guidelines in the PCI
Express* Isochronous/Virtual Channel Support Hardware Programming
Specification (HPS).
15:2 RO 0000h Reserved
1RO 0b
Link Type (LTYP)
This field indicates that the link points to memory-mapped space (for RCRB).
The link address specifies the 64-bit base address of the target RCRB.
0RW-O 0b
Link Valid (LV)
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 68–6Fh
Reset Value: 0000_0000_0000_0000h
Access: RO, RWO
Bit Attr
Reset
Value
Description
63:36 RO 0000000h Reserved: Reserved for Link Address high order bits.
35:12 RW-O 000000h
Link Address (LA)
This field provides the memory mapped base address of the RCRB that is the
target element (Egress Port) for this link entry.
11:0 RO 000h Reserved