Datasheet

Datasheet, Volume 2 155
Processor Configuration Registers
2.10.48 LSTS2—Link Status 2 Register
2.10.49 PEGLC—PCI Express* Legacy Control Register
This register controls functionality that is needed by Legacy (non-PCI Express aware)
OS's during run time.
B/D/F/Type: 0/1/0/PCI
Address Offset: D2–D3h
Reset Value: 0000h
Access: RO
Bit Attr
Reset
Value
Description
15:1 RO 0000h Reserved
0RO 0b
Current De-emphasis Level (CURDELVL)
1 = 3.5 dB
0 = 6 dB
When the link is operating at 2.5 GT/s speed, this bit is 0b.
B/D/F/Type: 0/1/0/PCI
Address Offset: EC–EFh
Reset Value: 0000_0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
31:3 RO
00000000
h
Reserved
2RW 0b
PME GPE Enable (PMEGPE)
0 = Do not generate GPE PME message when PME is received.
1 = Generate a GPE PME message when PME is received (Assert_PMEGPE
and Deassert_PMEGPE messages on DMI). This enables the MCH to
support PMEs on the PEG port under legacy OSs.
1RW 0b
Hot-Plug GPE Enable (HPGPE)
0 = Do not generate GPE Hot-Plug message when Hot-Plug event is
received.
1 = Generate a GPE Hot-Plug message when Hot-Plug Event is received
(Assert_HPGPE and Deassert_HPGPE messages on DMI). This enables
the MCH to support Hot-Plug on the PEG port under legacy OSs.
0RW 0b
General Message GPE Enable (GENGPE)
0 = Do not forward received GPE assert/de-assert messages.
1 = Forward received GPE assert/de-assert messages. These general GPE
message can be received using the PEG port from an external Intel
device (that is, PxH) and will be subsequently forwarded to the PCH
(using Assert_GPE and Deassert_GPE messages on DMI). For example,
PxH might send this message if a PCI Express device is hot plugged into
a PxH downstream port.