Datasheet

Datasheet, Volume 2 145
Processor Configuration Registers
5RW-SC 0b
Retrain Link (RL)
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer LTSSM
from L0, L0s, or L1 states to the Recovery state.
This bit always returns 0 when read. This bit is cleared automatically (no
need to write a 0).
4RW 0b
Link Disable (LD)
0 = Normal operation
1 = Link is disabled. Forces the LTSSM to transition to the Disabled state
(using Recovery) from L0, L0s, or L1 states. Link retraining happens
automatically on 0 to 1 transition, just like when coming out of reset.
Writes to this bit are immediately reflected in the value read from the bit,
regardless of actual Link state.
3RO 0b
Read Completion Boundary (RCB)
Hardwired to 0 to indicate 64 byte.
2RO 0bReserved (FEDLB):
1:0 RW 00b
Active State PM (ASPM)
This field controls the level of active state power management supported on
the given link.
00 = Disabled
01 = L0s Entry Supported
10 = L1 Entry Enabled
11 = L0s and L1 Entry Supported
Note: “L0s Entry Enabled” indicates the Transmitter entering L0s is
supported. The Receiver must be capable of entering L0s even when the field
is disabled (00b).
ASPM L1 must be enabled by software in the Upstream component on a Link
prior to enabling ASPM L1 in the Downstream component on that Link. When
disabling ASPM L1, software must disable ASPM L1 in the Downstream
component on a Link prior to disabling ASPM L1 in the Upstream component
on that Link. ASPM L1 must only be enabled on the Downstream component
if both components on a Link support ASPM L1.
B/D/F/Type: 0/1/0/PCI
Address Offset: B0–B1h
Reset Value: 0000h
Access: RO, RW, RW-SC
Bit Attr
Reset
Value
Description