Datasheet

Processor Configuration Registers

136 Datasheet, Volume 2

2.10.30 MSI_CAPID—Message Signaled Interrupts Capability ID

When a device supports MSI, it can generate an interrupt request to the processor by

writing a predefined data item (a message) to a predefined memory address.

The reporting of the existence of this capability can be disabled by setting MSICH

(CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and

instead go directly from the PCI PM capability to the PCI Express capability.

B/D/F/Type: 0/1/0/PCI

Address Offset: 90–91h

Reset Value: A005h

Access: RO

Bit Attr

Reset

Value

Description

15:8 RO A0h

Pointer to Next Capability (PNC)

This contains a pointer to the next item in the capabilities list which is the PCI

Express capability.

7:0 RO 05h

Capability ID (CID)

Value of 05h identifies this linked list item (capability structure) as being for

MSI registers.