Datasheet

Processor Configuration Registers
132 Datasheet, Volume 2
2.10.25 MSAC—Multi Size Aperture Control Register
This register determines the size of the graphics memory aperture in function 0 and in
the trusted space. Only the system BIOS will write this register based on pre- boot
address allocation efforts, but the graphics may read this register to determine the
correct aperture size. System BIOS needs to save this value on boot so that it can reset
it correctly during S3 resume.
1RW 0b
SERR Enable (SERREN)
0 = No forwarding of error messages from secondary side to primary side
that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR
message when individually enabled by the Root Control register.
0RW 0b
Parity Error Response Enable (PEREN)
Controls whether or not the Master Data Parity Error bit in the Secondary
Status register is set when the MCH receives across the link (upstream) a
Read Data Completion Poisoned TLP
0 = Master Data Parity Error bit in Secondary Status register can NOT be
set.
1 = Master Data Parity Error bit in Secondary Status register CAN be set.
B/D/F/Type: 0/1/0/PCI
Address Offset: 3E–3Fh
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
B/D/F/Type: 0/2/0/PCI
Address Offset: 62h
Reset Value: 02h
Access: RO, RW, RW-K
Bit Attr
Reset
Value
Description
7:4 RW 0h
Reserved: These RW bits are Scratch Bits Only. They have no physical effect
on hardware.
3 RO 0b Reserved
2:1 RW-K 01b
Untrusted Aperture Size (LHSAS)
11 = bits [28:27] of GMADR register are made Read only and forced to zero,
allowing only 512 MB of GMADR
01 = bit [28] of GMADR is made R/W and bit [27] of GMADR is forced to zero
allowing 256 MB of GMADR
00 = bits [28:27] of GMADR register are made RW allowing 128 MB of
GMADR
10 = Ivalid programming.
0RO 0hReserved