Datasheet

Processor Configuration Registers
128 Datasheet, Volume 2
2.10.18 PMLIMIT1—Prefetchable Memory Limit Address Register
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (that is, prefetchable) from the processor perspective.
2.10.19 PMBASEU1—Prefetchable Memory Base Address Upper
Register
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Base Address register
controls the processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
B/D/F/Type: 0/1/0/PCI
Address Offset: 26–27h
Reset Value: 0001h
Access: RW, RO
Bit Attr
Reset
Value
Description
15:4 RW 000h
Prefetchable Memory Address Limit (PMLIMIT)
This field corresponds to A[31:20] of the upper limit of the address range
passed to PCI Express-G.
3:0 RO 1h
64-bit Address Support
This field indicates that the upper 32 bits of the prefetchable memory region
limit address are contained in the Prefetchable Memory Base Limit Address
register at 2Ch
B/D/F/Type: 0/1/0/PCI
Address Offset: 28–2Bh
Reset Value: 0000_0000h
Access: RW
Bit Attr
Reset
Value
Description
31:0 RW
0000_000
0h
Prefetchable Memory Base Address (MBASEU)
This field corresponds to A[63:32] of the lower limit of the prefetchable
memory range that will be passed to PCI Express-G.