Datasheet

Processor Configuration Registers
124 Datasheet, Volume 2
2.10.14 SSTS1—Secondary Status Register
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI
bridge embedded within processor.
B/D/F/Type: 0/1/0/PCI
Address Offset: 1E–1Fh
Reset Value: 0000h
Access: RW1C, RO
Bit Attr
Reset
Value
Description
15 RW1C 0b
Detected Parity Error (DPE)
This bit is set by the Secondary Side for a Type 1 Configuration Space header
device whenever it receives a Poisoned TLP, regardless of the state of the
Parity Error Response Enable bit in the Bridge Control Register.
14 RW1C 0b
Received System Error (RSE)
This bit is set when the Secondary Side for a Type 1 configuration space
header device receives an ERR_FATAL or ERR_NONFATAL.
13 RW1C 0b
Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1 Configuration Space
Header Device (for requests initiated by the Type 1 Header Device itself)
receives a Completion with Unsupported Request Completion Status.
12 RW1C 0b
Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1 Configuration Space
Header Device (for requests initiated by the Type 1 Header Device itself)
receives a Completion with Completer Abort Completion Status.
11 RO 0b
Signaled Target Abort (STA)
Not Applicable or Implemented. Hardwired to 0. The processor does not
generate Target Aborts (the processor will never complete a request using
the Completer Abort Completion status).
10:9 RO 00b
DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hardwired to 0.
8RW1C 0b
Master Data Parity Error (SMDPE)
When set indicates that the MCH received across the link (upstream) a Read
Data Completion Poisoned TLP (EP=1). This bit can only be set when the
Parity Error Enable bit in the Bridge Control register is set.
7RO 0b
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
6RO 0bReserved
5RO 0b
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
4:0 RO 00h Reserved