Datasheet
Datasheet, Volume 2 119
Processor Configuration Registers
2.10.4 PCISTS1—PCI Status Register
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the processor.
B/D/F/Type: 0/1/0/PCI
Address Offset: 6–7h
Reset Value: 0010h
Access: RO, RW1C
Bit Attr
Reset
Value
Description
15 RO 0b
Detected Parity Error (DPE)
Not Applicable or Implemented. Hardwired to 0. Parity (generating poisoned
TLPs) is not supported on the primary side of this device (we don't do error
forwarding).
14 RW1C 0b
Signaled System Error (SSE)
This bit is set when this Device sends an SERR due to detecting an
ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the
Command register is '1'. Both received (if enabled by BCTRL1[1]) and
internally detected error messages do not affect this field.
13 RO 0b
Received Master Abort Status (RMAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a master
abort does not exist on primary side of this device.
12 RO 0b
Received Target Abort Status (RTAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a target abort
does not exist on primary side of this device.
11 RO 0b
Signaled Target Abort Status (STAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a target abort
does not exist on primary side of this device.
10:9 RO 00b
DEVSELB Timing (DEVT)
This device is not the subtractively decoded device on bus 0. This bit field is
therefore hardwired to 00 to indicate that the device uses the fastest possible
decode.
8RO 0b
Master Data Parity Error (PMDPE)
Because the primary side of the PEG's virtual P2P bridge is integrated with
the MCH functionality there is no scenario where this bit will get set. Because
hardware will never set this bit, it is impossible for software to have an
opportunity to clear this bit or otherwise test that it is implemented. The PCI
specification defines it as a R/WC, but for our implementation an RO
definition behaves the same way and will meet all Microsoft testing
requirements.
This bit can only be set when the Parity Error Enable bit in the PCI Command
register is set.
7RO 0b
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
6RO 0bReserved
5RO 0b
66/60MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
4RO 1b
Capabilities List (CAPL)
Indicates that a capabilities list is present. Hardwired to 1.
3RO 0b
INTA Status (INTAS)
Indicates that an interrupt message is pending internally to the device. Only
PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert
and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has
no effect on this bit.
Note that INTA emulation interrupts received across the link are not reflected
in this bit.
2:0 RO 000b Reserved