Datasheet

Datasheet, Volume 2 117
Processor Configuration Registers
2.10.1 VID1—Vendor Identification Register
This register combined with the Device Identification register uniquely identify any PCI
device.
2.10.2 DID1—Device Identification Register
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
2.10.3 PCICMD1—PCI Command Register
B/D/F/Type: 0/1/0/PCI
Address Offset: 0–1h
Reset Value: 8086h
Access: RO
Bit Attr
Reset
Value
Description
15:0 RO 8086h
Vendor Identification (VID1)
PCI standard identification for Intel.
B/D/F/Type: 0/1/0/PCI
Address Offset: 2–3h
Reset Value: 0041h
Access: RO
Bit Attr
Reset
Value
Description
15:4 RO 004h
Device Identification Number (DID1(UB))
Identifier assigned to the processor device 1 (virtual PCI-to-PCI bridge, PCI
Express Graphics port).
3:2 RO 00b
Device Identification Number (DID1(HW))
Identifier assigned to the processor device 1 (virtual PCI-to-PCI bridge, PCI
Express Graphics port).
1:0 RO 01b
Device Identification Number (DID1(LB))
Identifier assigned to the processor device 1 (virtual PCI-to-PCI bridge, PCI
Express Graphics port).
B/D/F/Type: 0/1/0/PCI
Address Offset: 4–5h
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:11 RO 00h Reserved
10 RW 0b
INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages. Any INTA
emulation interrupts already asserted must be de-asserted when this bit
is set. Only affects interrupts generated by the device (PCI INTA from a
PME or Hot Plug event) controlled by this command register. It does not
affect upstream MSIs, upstream PCI INTA-INTD assert and de-assert
messages.
9RO 0b
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0.