Datasheet

Datasheet, Volume 2 111
Processor Configuration Registers
2.9.3 EPVC0RCTL—EP VC 0 Resource Control Register
This register controls the resources associated with Egress Port Virtual Channel 0.
B/D/F/Type: 0/0/0/PXPEPBAR
Address Offset: 14–17h
Reset Value: 8000_00FFh
Access: RO, RW
Bit Attr
Reset
Value
Description
31 RO 1b
VC0 Enable (VC0E)
For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
30:27 RO 0h Reserved
26:24 RO 000b
VC0 ID (VC0ID)
Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read
only.
23:20 RO 0h Reserved
19:17 RW 000b
Port Arbitration Select (PAS)
This field configures the VC resource to provide a particular Port Arbitration
service. The value of 0h corresponds to the bit position of the only asserted
bit in the Port Arbitration Capability field.
16:8 RO 000h Reserved
7:1 RW 7Fh
TC/VC0 Map (TCVC0M)
This field indicates the TCs (Traffic Classes) that are mapped to the VC
resource. Bit locations within this field correspond to TC values. For example,
when bit 7 is set in this field, TC7 is mapped to this VC resource. When more
than one bit in this field is set, it indicates that multiple TCs are mapped to
the VC resource.
In order to remove one or more TCs from the TC/VC Map of an enabled VC,
software must ensure that no new or outstanding transactions with the TC
labels are targeted at the given Link.
0RO 1b
TC0/VC0 Map (TC0VC0M)
Traffic Class 0 is always routed to VC0.