Datasheet

Datasheet, Volume 2 107
Processor Configuration Registers
2.8.53 EXTTSCS—External Thermal Sensor Control and Status
Register
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 10EC–10EDh
Reset Value: 0000h
Access: RO, RW-O, RW-L
Bit Attr
Reset
Value
Description
15 RW-O 0b
External Sensor Enable (ESE)
Setting this bit to 1 locks the lockable bits in this register. This bit may only
be set to a zero by a hardware reset. Once locked, writing a 0 to bit has no
effect. EXTTS0 and EXTTS1 input signal pins are dedicated for external
thermal sensor use. An asserted External Thermal Sensor Trip signal can also
cause a SCI, SMI, SERR or INTR interrupt in the same manner as the Internal
Sensor can. A "0" on the pins can be used to trigger throttling. If both
internal sensor throttling and external sensor throttling are enabled, either
can initiate throttling. The AS0 and AS1 bits of this register allow control of
what action is triggered by external sensor trips. The processor Throttling
select bit controls the type of throttling action that will happen, and the
{AS0, AS1} bits control what trip actions will result.
0 = External Sensor input is disabled.
1 = External Sensor input is enabled.
14 RO 0b Reserved
13 RW-L 0b
Select between EXTTS PIN 0 and 1 (EXTTPINSEL)
0 = Use EXTTS Pin 0 for Thermal throttling, based of EXTTPMTRIP, EXTTFMX
and SD2X.
1 = Use EXTTS Pin 1 for the above.
12 RW-L 0b
EXTTS Based Power Monitor Trip (EXTTPMTRIP)
When this is set on extts, bit 0 can be programmed to look like a power-
monitor trip
1. will be OR’ed with the Global monitor/Gfx monitor so that, when
programmed for gfx throttle, when EXTTS# is asserted at the sample
point, it will look like a monitor trip and force RP down by the
programmed amount
2. EXTTS# is only sampled on the sampling window for graphics throttling,
so even if both the Gfx monitor and global monitor are disabled, the
sampling window must be programmed in order to have EXTTS# work
as a graphics throttle
11 RW-L 0b
Force DDR on EXTTS bit (EXTTFMX)
Enables forcing of DDR to specified MX state in registers EXTTSMXST when
the selected EXTTS bit 0 or 1(from exttpinsel field) is asserted.
Note: PMU looks at all enabled throttling and picks the highest value of Mx
for EXTTS#, or from the global power M state, or any other throttling and
passes it to the SD unit
10:8 RW-L 000b
EXTTSS Programmable MX state (EXTTSMXST)
MX state to which DDR to be forced to if EXTTS bit 0 asserts and Force DDR
on EXTTS bit (EXTTFMX) is enabled.
Note: PMU looks at all enabled throttling and picks the highest value of Mx
for EXTTS#, or from the global power M state, or any other throttling and
passes it to the SD unit.
7RW-L 0b
Force SD 2X Refresh Rate (SD2X)
When enabled on EXTTS bit 0 getting asserted will force memory into 2X
Refresh mode.