Datasheet
Processor Configuration Registers
106 Datasheet, Volume 2
2.8.52 TINTRCMD—Thermal INTR Command Register
This register selects specific errors to generate a INT DMI cycle.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 10E7h
Reset Value: 00h
Access: RO, RW
Bit Attr
Reset
Value
Description
7:6 RO 00b Reserved
5RW 0b
INTR on Catastrophic Thermal Sensor Trip (CATINTR)
1 = A INTR DMI cycle is generated by the processor
4RW 0b
INTR on Hot Thermal Sensor Trip (HOTINTR)
1 = A INTR DMI cycle is generated by the processor
3RW 0b
INTR on AUX3 Thermal Sensor Trip (AUX3INTR)
1 = A INTR DMI cycle is generated by the processor
2RW 0b
INTR on AUX2 Thermal Sensor Trip (AUX2INTR)
1 = A INTR DMI cycle is generated by the processor
1RW 0b
INTR on AUX1 Thermal Sensor Trip (AUX1INTR)
1 = A INTR DMI cycle is generated by the processor
0RW 0b
INTR on AUX0 Thermal Sensor Trip (AUX0INTR)
1 = A INTR DMI cycle is generated by the processor