Datasheet

Datasheet, Volume 2 101
Processor Configuration Registers
3RW1C 0b
Aux 3 Thermal Sensor Interrupt Event (A3TSIE)
1 = Aux 3 Thermal Sensor trip event occurred based on a lower to higher
temperature transition through the trip point.
0 = No trip for this event.
Software must write a 1 to clear this status bit.
2RW1C 0b
Aux 2 Thermal Sensor Interrupt Event (A2TSIE)
1 = Aux 2 Thermal Sensor trip event occurred based on a lower to higher
temperature transition thru the trip point.
0 = No trip for this event.
Software must write a 1 to clear this status bit.
1RW1C 0b
Aux 1 Thermal Sensor Interrupt Event (A1TSIE)
1 = Aux1 Thermal Sensor trip event occurred based on a lower to higher
temperature transition thru the trip point.
0 = No trip for this event.
Software must write a 1 to clear this status bit.
0RW1C 0b
Aux 0 Thermal Sensor Interrupt Event (A0TSIE)
1 = Aux 0 Thermal Sensor trip event occurred based on a lower to higher
temperature transition through the trip point.
0 = No trip for this event.
Software must write a 1 to clear this status bit.
The following scenario is possible. An interrupt is initiated on a rising
temperature trip, the appropriate DMI cycles are generated, and eventually
the software services the interrupt and sees a rising temperature trip as the
cause in the status bits for the interrupts. Assume that the software then
goes and clears the local interrupt status bit in the TIS register for that trip
event. It is possible at this point that a falling temperature trip event occurs
before the software has had the time to clear the global interrupts status bit.
But since software has already looked at the status register before this event
happened, software may not clear the local status flag for this event.
Therefore, after the global interrupt is cleared by software, software must
look at the instantaneous status in the TSS register.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 101E–101Fh
Reset Value: 0000h
Access: RO, RW1C
Bit Attr
Reset
Value
Description