Uncore Manual

Uncore Performance Monitoring
Uncore Per-Socket Performance Monitoring Control
16 Reference Number: 329468-002
e.g. Set C0_MSR_PMON_CTL2.en to 1
NOTE
Recommended: set the .en bit for all counters in each box a user intends to monitor,
and left alone for the duration of the monitoring session.
NOTE
For cases where there is no sharing of these counters among software agents indepen-
dently sampling the counters, software could set the enable bits for all counters it
intends to use during the setup phase. For cases where sharing is expected, each agent
could use the individual enable bits in order to perform sampling rather than using the
box-level freeze from steps (a) and (d).
c) Select event to monitor if the event control register hasn’t been programmed:
Program the .ev_sel and .umask bits in the control register with the encodings necessary to capture the
requested event along with any signal conditioning bits (.thresh/.edge_det) used to qualify the event.
e.g. Set C0_MSR_PMON_CT2.{ev_sel, umask} to {0x03, 0x1} in order to capture
LLC_VICTIMS.M_STATE in CBo 0’s C0_MSR_PMON_CTR2.
NOTE
It is also important to program any additional filter registers used to further qualify the
events (e.g. setting the opcode match field in Cn_MSR_BOX_FILTER to qualify
TOR_INSERTS by a specific opcode).
Back to the box level:
d) Reset counters in each box to ensure no stale values have been acquired from previous sessions.
Resetting the control registers, particularly those that won’t be used is also recommended if for no
other reason than to prevent errant overflows. To reset both the counters and control registers, write
the following registers:
• For each CBo, set Cn_MSR_PMON_BOX_CTL[1:0] to 0x3.
• Set HA_PCI_PMON_BOX_CTL[1:0] to 0x3.
NOTE
In the HA, when measuring an Occupancy count, it will be necessary to set the
.q_occ_rst bit to 1 in each control register set to measure an Occupancy count (e.g.
TRACKER_OCCUPANCY).
•For each Intel
®
QPI Port, set Q_Py_PCI_PMON_BOX_CTL[1:0] to 0x3.
• For each DRAM Channel, set MC_CHy_PCI_PMON_BOX_CTL[1:0] to 0x3.
• Set PCU_MSR_PMON_BOX_CTL[1:0] to 0x3.
• For each Link, set R3_Ly_PCI_PMON_BOX_CTL[1:0] to 0x3.
• Set R2_PCI_PMON_BOX_CTL[1:0] to 0x3.
NOTE
The UBox counters do not have a Box Control register. The counters will need to be
manually reset by writing a 0 in each data register.