Guide

Intel 852GM Platform Power Delivery Guidelines
R
Intel
®
852GM Chipset Platform Design Guide 229
12.5.4.2. GMCH AGTL+ I/O Buffer Compensation
The HXRCOMP and HYRCOMP pins of the GMCH should each be pulled-down to ground with a 27.4
Ω ± 1% resistor. See Figure 131. The maximum trace length from pin to resistor should be less than 0.5
inches and should be 18-mil wide to achieve the Zo = 27.4
Ω target. Also, the routing for HRCOMP
should be at least 25 mils away from any switching signal.
Figure 131. GMCH HXRCOMP and HYRCOMP Resistive Compensation
27.4
Ω
± 1%
HXRCOMP
27.4
Ω
± 1%
HYRCOMP
12.5.4.3. GMCH AGTL+ Reference Voltage
The GMCH’s AGTL+ I/O buffer resistive compensation mechanism also requires the generation of
reference voltages to the HXSWING and HYSWING pins with a value of 1/3*VCCP. Implementations
for HXSWING and HYSWING voltage generation are illustrated in Figure 132. Two resistive dividers
with R1a = R1b = 301
Ω ± 1% and R2a = R2b = 150 Ω ± 1% generate the HXSWING and HYSWING
voltages. C1a = C1b = 0.1 µF act as decoupling capacitors and connect HXSWING and HYSWING to
VCC_CORE. HSWING components should be placed within 0.5 inches of their respective pins and
connected with a 15-mil wide trace. To avoid coupling with any other signals, maintain a minimum of
25 mils of separation to other signals.
Figure 132. GMCH HXSWING and HYSWING Reference Voltage Generation Circuit
R1a
301
R2a
150
C1a
+VCCP
852GM
GMCH
HXSWING
HXSWING HYSWING
R1b
301
R2b
150
C1b
+VCCP
HYSWING
12.5.4.4. GMCH Analog Power
Table 94 summarizes the eight analog circuits that require filtered supplies on the GMCH. They are:
VCCASM, VCCQSM, VCCAHPLL, VCCADPLLA, VCCADPLLB, VCCADAC, VCCAGPLL, and