Specification Update
Summary Tables of Changes
Specification Update 11
Number D0 M0 Plans ERRATA
AN35 X X No Fix
Programming the Digital Thermal Sensor (DTS) Threshold May
Cause Unexpected Thermal Interrupts
AN36 Erratum removed
AN37 X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AN38 X Fixed BTS Message May be Lost when the STPCLK# Signal is Active
AN39 X Fixed
Certain Performance Monitoring Counters Related to Bus, L2 Cache
and Power Management are Inaccurate
AN40 X X No Fix
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AN41 X X No Fix
IO_SMI Indication in SMRAM State Save Area May be Set
Incorrectly
AN42 Erratum removed
AN43 Erratum removed
AN44 X Fixed Logical Processors May Not Detect Write-Back (WB) Memory Writes
AN45 X X No Fix LER MSRs May be Incorrectly Updated.
AN46 X Fixed
SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment
Selector” to SS and CS Registers
AN47 X X No Fix
Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
AN48 X X No Fix
Using 2M/4M pages When A20M# Is Asserted May Result in
Incorrect Address Translations
AN49 X Fixed
Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and
IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural
Performance Monitoring) Specification
AN50 X X No Fix
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AN51 X X No Fix
Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
AN52 X X No Fix
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Bit is Not Supported
AN53 X Fixed
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present
(P) Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
AN54 X Fixed
SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code
(SMC) Event May Cause Unexpected Behavior
AN55 No Fix Erratum Removed
AN56 X X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware
AN57 X X No Fix
Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering
Issue