Datasheet

6 Datasheet
Figure 8-22 BGA1288 Ballmap (Top View, Upper-Right Quadrant) ................................138
Figure 8-23 BGA1288 Ballmap (Top View, Lower-Left Quadrant) ..................................139
Figure 8-24 BGA1288 Ballmap (Top View, Lower-Right Quadrant) ................................140
Figure 8-25 rPGA Mechanical Package (Sheet 1 of 2) .................................................178
Figure 8-26 rPGA Mechanical Package (Sheet 2 of 2) ..................................................179
Figure 8-27 BGA Mechanical Package (Sheet 1 of 2) ...................................................181
Figure 8-28 BGA Mechanical Package (Sheet 2 of 2) ...................................................182
Tables
Table 2-1 Supported SO-DIMM Module Configurations1..............................................20
Table 2-2 DDR3 System Memory Timing Support ......................................................21
Table 2-3 eDP/PEG Ball Mapping.............................................................................33
Table 2-4 Processor Reference Clocks......................................................................35
Table 4-5 System States........................................................................................37
Table 4-6 Processor Core/Package State Support ......................................................37
Table 4-7 Integrated Memory Controller States.........................................................38
Table 4-8 PCIe Link States .....................................................................................38
Table 4-9 DMI States ............................................................................................38
Table 4-10 Integrated Graphics Controller States........................................................38
Table 4-11 G, S and C State Combinations.................................................................39
Table 4-12 D, S, and C State Combination .................................................................39
Table 4-13 Coordination of Thread Power States at the Core Level ................................42
Table 4-14 P_LVLx to MWAIT Conversion...................................................................42
Table 4-15 Coordination of Core Power States at the Package Level...............................45
Table 4-16 Targeted Memory State Conditions............................................................49
Table 5-17 Intel Pentium U5000 Mobile Processor Series Dual-Core ULV Thermal Power
Specifications.........................................................................................54
Table 5-18 Intel Pentium P6000 Mobile Processor Series Dual-Core SV Thermal Power
Specifications.........................................................................................55
Table 5-19 18 W Ultra Low Voltage (ULV) Processor Idle Power ....................................55
Table 5-20 35 W Standard Voltage (SV) Processor Idle Power.......................................56
Table 6-21 Signal Description Buffer Types ................................................................69
Table 6-22 Memory Channel A..................................................................................70
Table 6-23 Memory Channel B..................................................................................71
Table 6-24 Memory Reference and Compensation .......................................................72
Table 6-25 Reset and Miscellaneous Signals ...............................................................73
Table 6-26 PCI Express Graphics Interface Signals......................................................74
Table 6-27 Intel® Flexible Display Interface...............................................................75
Table 6-28 DMI - Processor to PCH Serial Interface .....................................................76
Table 6-29 PLL Signals ............................................................................................76
Table 6-30 TAP Signals............................................................................................77
Table 6-31 Error and Thermal Protection....................................................................78
Table 6-32 Power Sequencing ..................................................................................79
Table 6-33 Processor Power Signals ..........................................................................80
Table 6-34 Ground and NCTF ...................................................................................82
Table 6-35 Processor Internal Pull Up/Pull Down .........................................................82
Table 7-36 Voltage Identification Definition ................................................................85
Table 7-37 Market Segment Selection Truth Table for MSID[2:0] ..................................89
Table 7-38 Signal Groups1.......................................................................................90
Table 7-39 Processor Absolute Minimum and Maximum Ratings ....................................93
Table 7-40 Storage Condition Ratings........................................................................94