Datasheet

Introduction
8 Datasheet
1.2.4 cDVO
• Peak raw BW of 800MT/s
• Supports low power management schemes
• Supports AGTL+ interface
1.2.5 LVDS
• Maximum resolution (internal display) of:
• 1366 x 768 @ 18 bpp and 60 fps
• Dot clock range from 20–83 MHz
• Four differential signal pairs: Three data pairs (up to 581 Mbps on each data link)
and one clock pair
• Supports 18 bpp packed and 18 bpp loosely packed pixel formats
• Supports 24 bpp with a limited number of validated panels.
1.3 Terminology
Acronym Description
ACPI Advanced Configuration and Power Interface
AGTL+ Assisted Gunning Transceiver Logic Plus
CKE Clock enable
CMOS Complementary metal-oxide semiconductor
cDMI CMOS Direct Media Interface
cDVO CMOS Digital Video Output
DDR2 Second-generation Double Data Rate SDRAM memory technology
DQ Memory data
DQS Memory data strobe
DTS Digital thermal sensor
FSB Front side bus
GPIO General purpose input/output
GTL Gunning Transceiver Logic
HPLL Host phase lock loop
IERR Internal error
iFSB Internal front side bus
LFM Low Frequency Mode
LGI Legacy interface