Datasheet

4 Datasheet
6 Package Mechanical Specifications and Pin Information ............................... 37
6.1 Package Mechanical Specifications ........................................................... 37
6.2 Processor Pinout Assignment ................................................................... 39
Figures
Figure 3-1. Thread Low Power States .................................................................. 19
Figure 3-2. Package Low Power States ................................................................ 19
Figure 6-1. Package Mechanical Drawing ............................................................. 38
Tables
Table 2-1. Signal Types ..................................................................................... 11
Table 2-2. Buffer Types ..................................................................................... 11
Table 2-3. System Memory Interface Signals ....................................................... 11
Table 2-4. cDMI Interface Signal ........................................................................ 13
Table 2-5. cDVO Interface Signals ...................................................................... 13
Table 2-6. LVDS Display Port Interface Signals ..................................................... 14
Table 2-7. LGI/LGIe Legacy Signals .................................................................... 15
Table 2-8. Debug and Miscellaneous Signals ........................................................ 16
Table 2-9. Power Signals ................................................................................... 17
Table 4-1. VIDEN Encoding ................................................................................ 23
Table 4-2. VID Table ......................................................................................... 24
Table 4-3. Absolute Maximum Ratings ................................................................. 25
Table 4-4. Voltage and Current Specifications ...................................................... 26
Table 4-5. Differential Clock DC Specifications ...................................................... 28
Table 4-6. AGTL+, CMOS, and CMOS Open Drain Signal Group DC Specifications ..... 28
Table 4-7. CMOS1.8 Signal Group DC Specifications .............................................. 29
Table 4-8. LVDS Signal Group DC Specifications ................................................... 29
Table 5-1. Thermal Design Power Specifications ................................................... 31
Table 5-2. Support for PROCHOT#/THERMTRIP# in Active and Idle States ............... 34
Table 6-1. Processor Pinout (Top View—Columns 21–31) ....................................... 40
Table 6-2. Processor Pinout (Top View—Columns 11–20) ....................................... 41
Table 6-3. Processor Pinout (Top View—Columns 1–10) ........................................ 42
Table 6-4. Pinout—Ordered by Signal Name ......................................................... 43