Datasheet

Electrical Specifications
28 Datasheet
8. This is the sum of current on both rails.
9. Specification based on LVDS panel configuration of 1024x600 resolution, 60Hz refresh
rate, and 18bpp color depth.
Table 4-5. Differential Clock DC Specifications
Symbol Parameter Min. Typ. Max. Unit Notes
Differential Clock (BCLK)
V
IH
Input high voltage − − 1.15 V
V
IL
Input low voltage − − -0.3 V
V
CROSS
Crossing voltage 0.3 − 0.55 V
ΔV
CROSS
Range of crossing points − − 140 mV
V
SWING
Differential output swing 300 − − mV
I
LI
Input leakage current -5 − +5 µA
C
PAD
Pad capacitance 1.2 1.45 2.0 pF
Table 4-6. AGTL+, CMOS, and CMOS Open Drain Signal Group DC Specifications
Symbol Parameter Min. Typ. Max. Unit Notes
GTLREF GTL reference voltage − 2/3
V
CCP
− V
CMREF CMOS reference voltage − 1/2
V
CCP
− V
R
COMP
Compensation resistor 27.73 27.5 27.78 Ω 10
R
ODT
Termination resistor − 55 − Ω 11
V
IH
(GTL) Input high voltage GTL signal GTLREF
+ 0.10
V
CCP
V
CCP
+
0.10
V 3, 6
V
IL
(GTL) Input low voltage GTL signal -0.10 0 GTLREF
– 0.10
V 2, 4
V
IH
(CMOS) Input high voltage CMOS signal CMREF
+ 0.10
V
CCP
V
CCP
+
0.10
V 3, 6
V
IL
(CMOS) Input low voltage CMOS signal -0.10 0 CMREF
– 0.10
V 2, 4
V
OH
Output high voltage V
CCP
–
0.10
V
CCP
V
CCP
V 6
R
TT
(GTL) Termination resistance 46 55 61 Ω 7
R
TT
(CMOS) Termination resistance 46 55 61 Ω 11
R
ON
(GTL) GTL buffer on resistance 21 25 29 Ω 5
R
ON
(CMOS) CMOS buffer on resistance 42 50 55 Ω 12
R
ON
(CMOS_C)
CMOS common clock buffer on
resistance
42 50 58 Ω 12
I
LI
Input leakage current − − ±100 µA 8
C
PAD
Pad capacitance 1.6 2.1 2.55 pF 9