Datasheet

Power Management
Datasheet 21
• C4E
The C4E state is essentially the same as the C4 state except that the core
processor will transition to the Low Frequency Mode (LFM) frequency and voltage
upon entry and exit of this state.
• C6—Deep Power Down
Prior to entering the C6 state, the core processor will flush its cache and save its
core context to a special on-die SRAM on a different power plane. Once the C6
entry sequence has completed, the core processor's voltage can be completely shut
off.
The key difference for the North Complex logic between the C4 state and the C6
state is that since the core processor's cache is empty, there is no need to perform
snoops on the internal FSB. This means that bus master events (which would cause
a popup from the C4 state to the C2 state) can be allowed to flow unimpeded
during the C6 state. However, the core processor must still be returned to the C0
state to service interrupts.
A residency counter is read by the core processor to enable an intelligent
promotion/demotion based on energy awareness of transitions and history of
residencies/transitions.
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