Datasheet

Signal Descriptions
Datasheet 15
2.1.5 LGI/LGIe (Legacy) Signals
Table 2-7. LGI/LGIe Legacy Signals
Signal
Direction
Type
Description
VID[6:0]
O
CMOS
Voltage ID: Connects to PMIC. Indicates a desired voltage
for either V
CC
or V
NN
depending on the VIDEN[] pins.
Resolution of 12.5 mV.
VIDEN[1:0]
O
CMOS
Voltage ID enable: Connects to PMIC. Indicates which
voltage is being specified on the VID pins:
00 = VID is invalid
01 = VID = V
CC
10 = VID = V
NN
11 = RSVD
THERMTRIP#
O
CMOS_OD
Catastrophic Thermal Trip: The processor protects itself
from catastrophic overheating by use of an internal thermal
sensor. This sensor is set well above the normal operating
temperature to ensure that there are no false trips. The
processor will stop all execution when the junction
temperature exceeds approximately 120° C. This condition is
signaled to the system by the THERMTRIP# (Thermal Trip)
pin.
PROCHOT#
I/O
O:
CMOS_OD
I: CMOS
Processor hot: As an output, PROCHOT# (processor hot)
will go active when the processor temperature monitoring
sensor detects that the processor has reached its maximum
safe operating temperature. This indicates that the processor
Thermal Control Circuit (TCC) has been activated, if enabled.
As an input, assertion of PROCHOT# by the system will
activate the TCC, if enabled. The TCC will remain active until
the system de-asserts PROCHOT#.
VSSSENSE,
VCCSENSE,
VNNSENSE
O
Analog
Voltage sense: Connects to PMIC. Voltage Regulator must
connect feedback lines for V
CC
, V
SS
, and V
NN
to these pins on
the package.
BSEL1
O
CMOS
BSEL1: Selects external reference clock for DDR2, cDMI, and
cDVO frequencies.
1 = Reserved
0 = 100 MHz, for cDVO/DDR2-800MT/s.
IERR
O
CMOS
IERR: Internal error indication (debug). Positively asserted.
Asserted when the processor has had an internal error and
may have unexpectedly stopped executing. Assertion of IERR
is usually accompanied by a SHUTDOWN transaction internal
to Processor which may result in assertion of NMI to the
processor. The processor will keep IERR asserted until the
POWERMODE[] pins take Processor to reset or Processor
receives a reset message over cDMI.
GTLREF0
I
Analog
Voltage reference for BPM[3:0]#: 2/3 V
CCP
by means of an
external voltage divider: 1k Ω to V
CCP
, 2 KΩ to V
SS
.
GTLREF1
I
Analog
Voltage reference: 2/3 V
CCP
by means of external voltage
divider: 1 KΩ to V
CCP
, 2 KΩ to V
SS
.