Datasheet

Signal Descriptions
12 Datasheet
Signal
Direction
Type
Description
SM_SREN#
I
CMOS1.8
Self-refresh enable: Signal from the chipset asserted after
processor places DDR in self-refresh.
SM_CKE[1:0]
O
CMOS1.8
Clock enable: SM_CKE is used for power control of the DRAM
devices. There is one SM_CKE per rank.
SM_CS[1:0]#
O
CMOS1.8
Chip select: These signals determine whether a command is
valid in a given cycle for the devices connected to it. There is
one chip select signal for each rank.
SM_RAS#
O
CMOS1.8
Row address strobe: This signal is used with SM_CAS# and
SM_WE# (along with SM_CS#) to define commands.
SM_CAS#
O
CMOS1.8
Column address strobe: This signal is used with SM_WE#,
SM_RAS#, and SM_CS# to define commands.
SM_WE#
O
CMOS1.8
Write enable: This signal is used with SM_CAS#, SM_RAS#,
and SM_CS# to define commands.
SM_ODT[1:0]
O
CMOS1.8
On Die Termination: Active Termination Control.
SM_BS[2:0]
O
CMOS1.8
Bank select: These signals define which banks are being
addressed within each Rank.
SM_MA[14:0]
O
CMOS1.8
Multiplexed address: SM_MA signals provide multiplexed row
and column address to memory.
SM_DQ[31:0]
I/O
CMOS1.8
Data lines: SM_DQ signals interface to the DRAM data bus.
SM_DQS[3:0]
I/O
CMOS1.8
Data strobes: These signals are used during writes and are
centered with respect to data. During reads, these signals are
driven by memory devices and are edge aligned with data.
SM_DM[3:0]
O
CMOS1.8
Data mask: One bit per byte indicating which bytes should be
written.
SM_RCVENIN
I
CMOS1.8
Receive enable in: This input enables the SM_DQS input
buffers during reads.
SM_RCVENOUT
O
CMOS1.8
Receive enable out: Part of the feedback used to enable the
DQS input buffers during reads.
SM_RCOMP
I
Analog
RCOMP: Connected to high-precision resistor on the
motherboard. Used to dynamically calibrate the driver strengths.