Datasheet

Electrical Specifications
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012 Datasheet - Volume 1 of 2
Document Number: 327405
-001 99
9.10.2 Platform Environmental Control Interface DC Specifications
Platform Environmental Control Interface (PECI) is an Intel proprietary interface that
provides a communication channel between Intel processors and chipset components
to external Adaptive Thermal Monitor devices. The processor contains a Digital Thermal
Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control
Circuit (TCC) activation temperature. Temperature sensors located throughout the die
are implemented as analog-to-digital converters calibrated at the factory. PECI
provides an interface for external devices to read the DTS temperature for thermal
management and fan speed control.
9.10.2.1 PECI Bus Architecture
The PECI architecture is based on a wired-OR bus, which the processor PECI can pull up
high (with strong drive strength). The idle state on the bus is near zero.
Figure 9-1 demonstrates PECI design and connectivity. The host/originator can be a
third-party PECI host, with one of the PECI clients being the processor PECI device.
Table 9-12. PCI Express* DC Specifications
Symbol Parameter Min Typ Max Units Notes
1
V
TX-DIFF-p-p
Differential Peak-to-Peak Tx Voltage Swing 0.4 0.5 0.6 V 4
V
TX_CM-AC-p
Tx AC Peak Common Mode Output Voltage (Gen 1
Only)
0.8 1 1.2 mV 1,2,5
Z
TX-DIFF-DC
DC Differential Tx Impedance (Gen 1 Only) 80 120 Ω 1,9
Z
RX-DC
DC Common Mode Rx Impedance 40 60 Ω 1,7,8
Z
RX-DIFF-DC
DC Differential Rx Impedance (Gen1 Only) 80 120 Ω 1
V
RX-DIFFp-p
Differential Rx Input Peak-to-Peak Voltage (Gen 1
only)
0.175 1.2 V 1,3,10
V
RX_CM-AC-p
Rx AC Peak Common Mode Input Voltage 150 mV 1,6
Notes:
1. See the PCI Express* Base Specification for details.
2. V
TX-AC-CM-PP
and V
TX-AC-CM-P
are defined in the PCI Express Base Specification. Measurement is made over at least 10^
6
UI.
3. See Figure 9-8, “PCI Express* Receiver Eye Margins” on page 113.
4. As measured with compliance test load. Defined as 2*|V
TXD+
- V
TXD-
|.
5. RMS value.
6. Measured at Rx pins into a pair of 50-Ω terminations into ground. Common mode peak voltage is defined by the
expression: max{|(Vd+ - Vd-) - V-CMDC|}.
7. DC impedance limits are needed to guarantee Receiver detect.
8. The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that
the Receiver Detect occurs properly. Compensation of this impedance can start immediately and the 15 Rx Common
Mode Impedance (constrained by RLRX-CM to 50 Ω ±20%) must be within the specified range by the time Detect is
entered.
9. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
10. This specification is the same as V
RX-EYE.