Datasheet
Electrical Specifications
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2 May 2012
98 Document Number: 327405
-001
R
ON_DN(CMD)
DDR3 Command Buffer pull-down
Resistance
15.7 19.8 24.0 Ω 5
R
ON_UP(CTL)
DDR3 Control Buffer pull-up
Resistance
14.9 20.1 23.7 Ω 5
R
ON_DN(CTL)
DDR3 Control Buffer pull-down
Resistance
14.5 19.2 24.3 Ω 5
I
LI
Input Leakage Current (DQ, CK)
0V
0.2*V
DDQ
0.8*V
DDQ
V
DDQ
± 0.75
± 0.55
± 0.9
± 1.4
mA
I
LI
Input Leakage Current (CMD, CTL)
0V
0.2*V
DDQ
0.8*V
DDQ
V
DDQ
± 0.85
± 0.65
± 1.10
± 1.65
mA
SM_RCOMP0 Command COMP Resistance 138.6 140 141.4 Ω 8
SM_RCOMP1 Data COMP Resistance 25.74 26 26.26 Ω 8
SM_RCOMP2 ODT COMP Resistance 198 200 202 Ω 8
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
DDQ
. However, input signal drivers must comply with the signal quality
specifications.
5. This is the pull up/down driver resistance. See the processor I/O Buffer Models for I/V characteristics.
6. R
TERM
is the termination on the DIMM and is not controlled by the Processor.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx resistors are connected
to V
SS
.
9. SM_DRAMPWROK must have a maximum of 15ns rise or fall time over V
DDQ
* 0.55± 200mV and the edge must be
monotonic.
10. SM_VREF is defined as V
DDQ
/2
Table 9-11. Control Sideband and TAP Signal Group DC Specifications
Symbol Parameter Min Max Units Notes
1
V
IL
Input Low Voltage V
CCIO
*0.3 V 2,3
V
IH
Input High Voltage V
CCIO
*0.7 V 2,3,5
V
OL
Output Low Voltage V
CCIO
*0.1 V 2
V
OH
Output High Voltage V
CCIO
*0.9 V 2,5
R
ON
Buffer on Resistance 23 73 Ω
I
LI
Input Leakage Current
- PROCHOT#
- TDO
- All other signals in this group
-0.20 to +2.00
-0.20 to +2.00
-0.20 to +0.50
mA 4
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
CCIO
referred to in these specifications refers to instantaneous V
CCIO
.
3. See the processor I/O Buffer Models for I/V characteristics.
4. For V
IN
between “0” V and V
CCIO
. Measured when the driver is tristated.
5. V
IH
and V
OH
may experience excursions above V
CCIO
. However, input signal drivers must comply with the signal quality
specifications.
Table 9-10. DDR3 Signal Group DC Specifications (Sheet 2 of 2)
Symbol Parameter Min Typ Max Units Notes
1