Datasheet

Electrical Specifications
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012 Datasheet - Volume 1 of 2
Document Number: 327405
-001 91
DDR3 Data Signals
2
Single ended DDR3 Bi-directional
SA_DQ[63:0], SB_DQ[63:0]
SA_ECC_CB[7:0],
SB_ECC_CB[7:0]
Differential DDR3 Bi-directional
SA_DQS[8:0], SA_DQS#[8:0]
SB_DQS[8:0], SB_DQS#[8:0]
DDR3 Compensation
Analog Bi-directional SM_RCOMP[2:0]
DDR3 Reference
Analog Input SM_VREF
TAP (ITP/XDP)
Single Ended CMOS Input TCK, TDI, TMS, TRST#
Single Ended CMOS Open-Drain Output TDO
Single Ended Asynchronous CMOS Bi-directional BPM#[7:0]
Single Ended Asynchronous CMOS Output PRDY#
Single Ended Asynchronous CMOS Input PREQ#
Control Sideband
3
Single Ended CMOS Input CFG[17:0]
Single Ended Asynchronous GTL Bi-directional PROCHOT#
Single Ended Asynchronous CMOS Output THERMTRIP#, CATERR#
Single Ended Asynchronous CMOS Input
SM_DRAMPWROK,
UNCOREPWRGOOD
4
, PM_SYNC,
RESET#
Single Ended Asynchronous Bi-directional PECI
Voltage Regulator
Single Ended CMOS Input VIDALERT#
Single Ended Open Drain Output VIDSCLK
Single Ended CMOS Output VCCSA_VID
Single Ended
Bi-directional CMOS Input/Open
Drain Output
VIDSOUT
Single Ended Analog Output
VCCSA_VCCSENCE,
VCCSA_VSSSENCE,
Differential Analog Output
VCC_SENSE, VSS_SENSE,
VCCIO_SENSE,
VSS_SENSE_VCCIO,
Power/Ground/Other
Single Ended
Power V
CC
, V
CCIO
, V
CCSA
, V
CCPLL
, V
DDQ
Ground V
SS
No Connect /Test Point RSVD
Other PROC_DETECT#
Table 9-3. Signal Groups (Sheet 2 of 3)
Signal Group
1
Type Signals