Datasheet

Signal Description
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2 May 2012
74 Document Number: 327405
-001
8.2 Memory Reference and Compensation
8.3 Reset and Miscellaneous Signals
Table 8-4. Memory Reference and Compensation
Signal Name Description
Direction/Buffer
Type
SM_RCOMP[2:0]
System Memory Impedance Compensation:
SM_RCOMP[0] Pull Down to VSS via 140 Ω ±1%
SM_RCOMP[1] Pull Down to VSS via 25.5 Ω ±1%
SM_RCOMP[2] Pull Down to VSS via 200 Ω ±1%
I/Analog
SM_VREF
DDR3 Reference Voltage: This provides
reference voltage to the DDR3 interface and is
defined as VDDQ/2
I/Analog
Table 8-5. Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name Description
Direction/Buffer
Type
CFG[17:0]
Configuration Signals:
The CFG signals have a default value of '1' if not
terminated on the board. See the appropriate
Platform Design Guide for pull-down
recommendations when a logic low is desired.
• CFG[1:0]: Reserved configuration ball. A test
point may be placed on the board for this ball.
• CFG[2]: PCI Express* Static x16 Lane (Port1)
Numbering Reversal.
— 1 = Normal operation (default)
— 0 = Lane numbers reversed
• CFG[3]: PCI Express* Static x4 Lane (Port2)
Numbering Reversal.
— 1 = Normal operation (default)
— 0 = Lane numbers reversed
• CFG[4]: Reserved configuration ball. A test
point may be placed on the board for this ball.
• CFG[6:5]: PCI Express* Bifurcation:
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[17:7]: Reserved configuration balls. A test
point may be placed on the board for these balls.
Note: These strap values are read upon power up
and the pre-boot software enables the
appropriate number of controllers and lane
orientation. See Section 3.2.5,
“Configuring PCIe* Lanes” and Section
3.2.6, “Lane Reversal on PCIe* Interface”
for further details.
I
CMOS
PM_SYNC
Power Management Sync: A sideband signal to
communicate power management status from the
platform to the processor.
I
CMOS
RESET#
Platform Reset pin driven by the PCH
I
CMOS