Datasheet

Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012 Datasheet - Volume 1 of 2
Document Number: 327405-001 7
Contents
3-5 PCI Express* PCI Port Bifurcation.........................................................................33
3-6 PCIe* Typical Operation 16 Lanes Mapping............................................................34
6-1 Power States .....................................................................................................47
6-2 Idle Power Management Breakdown of the Processor Cores .....................................50
6-3 Thread and Core C-State Entry and Exit ................................................................51
6-4 Package C-State Entry and Exit............................................................................55
7-1 Frequency and Voltage Ordering...........................................................................64
9-1 Example of PECI Host-Client Connection.............................................................. 100
9-2 Input Device Hysteresis .................................................................................... 101
9-3 Differential Clock – Differential Measurements...................................................... 110
9-4 Differential Clock – Single Ended Measurements................................................... 111
9-5 DDR3 Command / Control and Clock Timing Waveform ......................................... 111
9-6 DDR3 Receiver Eye Mask................................................................................... 112
9-7 DDR3 Clock to DQS Skew Timing Waveform ........................................................ 112
9-8 PCI Express* Receiver Eye Margins..................................................................... 113
9-9 TAP Valid Delay Timing Waveform ...................................................................... 113
9-10 Test Reset (TRST#), Async Input, and PROCHOT# Timing Waveform ...................... 114
9-11 THERMTRIP# Power Down Sequence .................................................................. 114
9-12 VCC Overshoot Example Waveform..................................................................... 116
9-13 Maximum Acceptable Overshoot/Undershoot Waveform......................................... 117
10-1 Ball Map (Bottom View, Upper Left Side) ............................................................. 142
10-2 Ball Map (Bottom View, Upper Right Side) ........................................................... 143
10-3 Ball Map (Bottom View, Lower Left Side) ............................................................. 144
10-4 Ball Map (Bottom View, Lower Right Side) ........................................................... 145
10-5 Processor 4-Core Die Mechanical Package............................................................ 147
10-6 Processor 2-Core Die / 1-Core Die Mechanical Package.......................................... 148
Tables
1-1 Processor Documents .........................................................................................11
1-2 Cave Creek PCH Documents ................................................................................12
1-3 Public Specifications ...........................................................................................12
1-4 Terminology ......................................................................................................13
3-1 Supported UDIMM Module Configurations1, 2.........................................................24
3-2 Supported SO-DIMM Module Configurations1, 2......................................................25
3-3 Supported Memory Down Configurations 1 ............................................................26
3-4 DDR3 System Memory Timing Support..................................................................27
3-5 Hardware Straps for PCIe* Controller Enabling (Port 1 Only)....................................35
3-6 Hardware Straps for Normal/Reversed Operation of PCIe* Lanes..............................36
3-7 Reference Clock.................................................................................................37
5-1 Base Features by SKU.........................................................................................45
6-1 System States ...................................................................................................48
6-2 Processor Core/Package State Support..................................................................48
6-3 Integrated Memory Controller States ....................................................................48
6-4 PCIe* Link States...............................................................................................49
6-5 DMI States........................................................................................................49
6-6 G, S and C State Combinations ............................................................................49
6-7 Coordination of Thread Power States at the Core Level............................................51
6-8 P_LVLx to MWAIT Conversion...............................................................................52
6-9 Coordination of Core Power States at the Package Level..........................................54
7-1 TDP Specifications..............................................................................................62
7-2 Junction Temperature Specification.......................................................................62
8-1 Signal Description Buffer Types............................................................................71
8-2 Memory Channel A .............................................................................................71
8-3 Memory Channel B .............................................................................................72