Datasheet

Contents
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2 May 2012
6 Document Number: 327405-001
9.0 Electrical Specifications ...........................................................................................81
9.1 Power and Ground Pins.......................................................................................81
9.2 Decoupling Guidelines ........................................................................................81
9.2.1 Voltage Rail Decoupling ...........................................................................81
9.3 Processor Clocking (BCLK, BCLK#).......................................................................82
9.3.1 PLL Power Supply ...................................................................................82
9.4 Serial Voltage Identification (SVID)......................................................................82
9.5 System Agent (SA) Vcc VID ................................................................................89
9.6 Reserved or Unused Signals................................................................................90
9.7 Signal Groups ...................................................................................................90
9.8 Test Access Port (TAP) Connection.......................................................................92
9.9 Storage Conditions Specifications.........................................................................92
9.10 DC Specifications...............................................................................................93
9.10.1 Voltage and Current Specifications............................................................94
9.10.2 Platform Environmental Control Interface DC Specifications..........................99
9.11 AC Specifications.............................................................................................101
9.11.1 DDR3 AC Specifications .........................................................................103
9.11.2 PCI Express* AC Specification ................................................................107
9.11.3 Miscellaneous AC Specifications ..............................................................108
9.11.4 TAP Signal Group AC Specifications.........................................................108
9.11.5 SVID Signal Group AC Specifications .......................................................109
9.12 Processor AC Timing Waveforms........................................................................109
9.13 Signal Quality..................................................................................................114
9.13.1 Input Reference Clock Signal Quality Specifications ...................................115
9.13.2 DDR3 Signal Quality Specifications..........................................................115
9.13.3 I/O Signal Quality Specifications .............................................................115
9.14 Overshoot/Undershoot Guidelines ......................................................................115
9.14.1 VCC Overshoot Specification ..................................................................115
9.14.2 Overshoot/Undershoot Magnitude ...........................................................116
9.14.3 Overshoot/Undershoot Pulse Duration .....................................................116
10.0 Processor Ball and Package Information................................................................119
10.1 Processor Ball Assignments...............................................................................119
10.2 Package Mechanical Information........................................................................146
11.0 Processor Configuration Registers .........................................................................151
11.1 ERRSTS - Error Status......................................................................................152
11.2 ERRCMD - Error Command................................................................................153
11.3 SMICMD - SMI Command..................................................................................154
11.4 SCICMD - SCI Command ..................................................................................155
11.5 ECCERRLOG0_C0 - ECC Error Log 0 ...................................................................155
11.6 ECCERRLOG1_C0 - ECC Error Log 1 ...................................................................156
11.7 ECCERRLOG0_C1 - ECC Error Log 0 ...................................................................157
11.8 ECCERRLOG1_C1 - ECC Error Log 1 ...................................................................158
11.9 MAD_DIMM_CH0 - Address Decode Channel 0 .....................................................158
11.10 MAD_DIMM_CH1 - Address Decode Channel 1 .....................................................160
11.11 Error Detection and Correction ..........................................................................161
Figures
2-1 Crystal Forest Platform Example Block Diagram ......................................................16
3-1 Intel® Flex Memory Technology Operation.............................................................28
3-2 PCI Express* Layering Diagram............................................................................30
3-3 Packet Flow through the Layers............................................................................31
3-4 PCI Express* Related Register Structures...............................................................32