Datasheet

Power Management
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012 Datasheet - Volume 1 of 2
Document Number: 327405
-001 53
6.2.4.3 Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
6.2.4.4 Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
6.2.4.5 Core C7 State
Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to
the P_BLK or by an MWAIT(C7) instruction. The core C7 state exhibits the same
behavior as the core C6 state unless the core is the last one in the package to enter the
C7 state. If it is, that core is responsible for flushing L3 cache ways. The processor
supports the C7s substate. When an MWAIT(C7) command is issued with a C7s
sub-state hint, the entire L3 cache is flushed one step as opposed to flushing the L3
cache in multiple steps.
Note: Core C7 State support is available for Quad and Dual Core processors. Single Core
processors do not support Core C7 State.
6.2.4.6 C-State Auto-Demotion
In general, deeper C-states such as C6 or C7 have long latencies and have higher
energy entry/exit costs. The resulting performance and energy penalties become
significant when the entry/exit frequency of a deeper C-state is high. Therefore
incorrect or inefficient usage of deeper C-states have a negative impact on power. In
order to increase residency and improve power in deeper C-states, the processor
supports C-state auto-demotion.
There are two C-State auto-demotion options:
• C6/C7 to C3
• C7/C6/C3 To C1
The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 is based on each
core’s immediate residency history. Upon each core C6/C7 request, the core C-state is
demoted to C3 or C1 until a sufficient amount of residency has been established. At
that point, a core is allowed to go into C3/C6 or C7. Each option can be run
concurrently or individually.
This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
6.2.5 Package C-States
The processor supports C0, C1/C1E, C3, C6, and C7 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package C-
states unless specified otherwise: