Datasheet

Power Management
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2 May 2012
52 Document Number: 327405
-001
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note: When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF’ feature which triggers a wakeup
on an interrupt even if interrupts are masked by EFLAGS.IF.
6.2.4 Core C-states
The following are general rules for all core C-states, unless specified otherwise:
• A core C-State is determined by the lowest numerical thread state (e.g., Thread 0
requests C1E while Thread 1 requests C3, resulting in a core C1E state). See
Table 6-6, “G, S and C State Combinations”.
• A core transitions to C0 state when:
— An interrupt occurs
— There is an access to the monitored address if the state was entered via an
MWAIT instruction
• For core C1/C1E, and core C3, and core C6/C7, an interrupt directed toward a
single thread wakes only that thread. However, since both threads are no longer at
the same core C-state, the core resolves to C0.
• A system reset re-initializes all processor cores.
6.2.4.1 Core C0 State
The normal operating state of a core where code is being executed.
6.2.4.2 Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel
®
64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see Section 6.2.5.2, “Package C1/C1E”.
Table 6-8. P_LVLx to MWAIT Conversion
P_LVLx MWAIT(Cx) Notes
P_LVL2 MWAIT(C3) The P_LVL2 base address is defined in the PMG_IO_CAPTURE MSR.
P_LVL3 MWAIT(C6) C6. No sub-states allowed.
P_LVL4 MWAIT(C7) C7. No sub-states allowed.
P_LVL5+ MWAIT(C7) C7. No sub-states allowed.