Datasheet

Technologies
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012 Datasheet - Volume 1 of 2
Document Number: 327405
-001 41
• MSI cycles (MemWr to address FEEx_xxxxh) not translated
— Translation faults result in cycle forwarding to VBIOS region (byte enables
masked for writes). Returned data may be bogus for internal agents, PEG/DMI
interfaces return unsupported request status
• Interrupt Remapping is supported
• Queued invalidation is supported.
• VT-d translation bypass address range is supported (Pass Through)
• Support for ARI (Alternative Requester ID - a PCI SIG ECR for increasing the
function number count in a PCIe device) to support IOV devices.
4.1.5 Intel
®
VT-d Features Not Supported
The following features are not supported by the processor with Intel
®
VT-d:
• No support for PCISIG endpoint caching (ATS)
• No support for Intel
®
VT-d read prefetching/snarfing i.e. translations within a
cacheline are not stored in an internal buffer for reuse for subsequent translations.
• No support for advance fault reporting
• No support for super pages
• No support for Intel
®
VT-d translation bypass address range (such usage models
need to be resolved with VMM help in setting up the page tables correctly)
4.2 Intel
®
Hyper-Threading Technology
The processor supports Intel
®
Hyper-Threading Technology (Intel
®
HT Technology),
which allows an execution core to function as two logical processors. While some
execution resources such as caches, execution units, and buses are shared, each
logical processor has its own architectural state with its own set of general-purpose
registers and control registers. This feature must be enabled via the BIOS and requires
operating system support.
Intel recommends enabling Hyper-Threading Technology with Microsoft Windows 7*,
Microsoft Windows Vista*, Microsoft Windows* XP Professional/Windows* XP Home,
and disabling Hyper-Threading Technology via the BIOS for all previous versions of
Windows operating systems. For more information on Hyper-Threading Technology, see
http://www.intel.com/technology/platform-technology/hyper-threading/.
4.3 Intel
®
Advanced Vector Extensions (Intel
®
AVX)
Intel
®
Advanced Vector Extensions (Intel
®
AVX) is the latest expansion of the Intel
instruction set. It extends the Intel
®
Streaming SIMD Extensions (SSE) from 128-bit
vectors into 256-bit vectors. Intel
®
AVX addresses the continued need for vector
floating-point performance in mainstream scientific and engineering numerical
applications, visual processing, recognition, data-mining/synthesis, gaming, physics,
cryptography and other areas of applications. The enhancement in Intel
®
AVX allows
for improved performance due to wider vectors, new extensible syntax, and rich
functionality including the ability to better manage, rearrange, and sort data. For more
information on Intel
®
AVX, see http://www.intel.com/software/avx.