Datasheet
Contents
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2 May 2012
4 Document Number: 327405-001
Contents
1.0 Introduction ............................................................................................................11
1.1 Purpose / Scope / Audience.................................................................................11
1.2 Related Documents............................................................................................11
1.3 Terminology......................................................................................................13
2.0 Product Overview ....................................................................................................15
2.1 Product Features ...............................................................................................17
2.2 Processor Details...............................................................................................17
2.3 Supported Technologies......................................................................................17
2.4 Interface Features .............................................................................................17
2.4.1 System Memory Support .........................................................................17
2.4.2 PCI Express*..........................................................................................18
2.4.3 Direct Media Interface (DMI)....................................................................20
2.4.4 Platform Environment Control Interface (PECI) ...........................................20
2.5 Power Management Support................................................................................21
2.5.1 Processor Core .......................................................................................21
2.5.2 System .................................................................................................21
2.5.3 Memory Controller..................................................................................21
2.5.4 PCI Express*..........................................................................................21
2.5.5 DMI ......................................................................................................21
2.6 Thermal Management Support.............................................................................21
2.7 Package ...........................................................................................................21
2.8 Testability.........................................................................................................21
3.0 Interfaces................................................................................................................23
3.1 System Memory Interface...................................................................................23
3.1.1 System Memory Configurations Supported.................................................23
3.1.2 System Memory Timing Support ...............................................................26
3.1.3 System Memory Organization Modes .........................................................27
3.1.4 Rules for Populating Memory Slots ............................................................28
3.1.5 Technology Enhancements of Intel
®
Fast Memory Access (Intel
®
FMA)..........28
3.1.6 Data Scrambling.....................................................................................29
3.1.7 DRAM Clock Generation...........................................................................29
3.2 PCI Express* Interface .......................................................................................29
3.2.1 PCI Express* Architecture........................................................................30
3.2.2 PCI Express* Configuration Mechanism......................................................32
3.2.3 PCI Express* Port Bifurcation ...................................................................32
3.2.4 PCI Express* Lanes Connection ................................................................34
3.2.5 Configuring PCIe* Lanes..........................................................................35
3.2.6 Lane Reversal on PCIe* Interface..............................................................36
3.3 Direct Media Interface........................................................................................36
3.3.1 DMI Error Flow.......................................................................................36
3.3.2 Processor/PCH Compatibility Assumptions..................................................36
3.3.3 DMI Link Down.......................................................................................36
3.4 Platform Environment Control Interface (PECI) ......................................................37
3.5 Interface Clocking..............................................................................................37
3.5.1 Internal Clocking Requirements ................................................................37
4.0 Technologies............................................................................................................39
4.1 Intel
®
Virtualization Technology ..........................................................................39
4.1.1 Intel
®
VT-x Objectives ............................................................................39
4.1.2 Intel
®
VT-x Features...............................................................................39
4.1.3 Intel
®
VT-d Objectives ............................................................................40