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Datasheet - Volume 1 of 2 May 2012
32 Document Number: 327405
-001
3.2.2 PCI Express* Configuration Mechanism
All of the PCI Express* controllers are mapped through a PCI-to-PCI bridge structure.
The controllers for the 16 lanes (Port 1) are mapped to the root port of Device 1:
• The x16 controller is mapped to Function 0
• The x8 controller is mapped to Function 1
• The x4 controller is mapped to Function 2
The additional x4 controller for lanes (Port 2) is mapped to Device 6 Function 0. Port 2
is not available on 1 Core SKUs. (see Table 5-1, “Base Features by SKU”)
3 of the 4 controllers create Port 1 and can automatically operate on lower lane width
modes allowing up to 3 simultaneous operating devices on these 16 lanes. Bifurcation
details are described in Section 3.2.3, “PCI Express* Port Bifurcation”, and the
hardware straps required to enable the x16, x8 and the x4 controllers are described in
Section 3.2.4, “PCI Express* Lanes Connection”.
The fourth controller is a single dedicated controller, which creates the x4 Port 2 that
enumerates on Device 6. Port 2 can be configured to operate in 1x4, 1x2 or 1x1 mode,
but there are no hardware straps.
Note: The controllers in Port 1 cannot be used to function with the controller in Port 2.
Therefore, the x16 lanes of Port 1 must not be combined with the x4 lanes of Port 2.
3.2.3 PCI Express* Port Bifurcation
Only the 3 controllers on Port 1 can be bifurcated. When bifurcated, the wires which
had previously been assigned to lanes [15:8] of the single x16 primary port are
reassigned to lanes [7:0] of the x8 secondary controller (Function 1). This assignment
applies whether the lane numbering is reversed or not. Further bifurcation of Port 1 is
possible through the third contoller (Function 2) to create two x4 PCI Express*.
When Port 1 is not bifurcated, Function 1 and Function 2 are hidden from the discovery
mechanism used in PCI enumeration.
The controls for Port 2 and the associated virtual PCI-to-PCI bridge can be found in PCI
Device 6, which provides an additional x4 Port.
Figure 3-4. PCI Express* Related Register Structures