Datasheet

Product Overview
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2 May 2012
18 Document Number: 327405
-001
• 72-bit wide channels, 64-bit data + 8-bit ECC
• 64-bit wide channels, without ECC option
• DDR3 I/O Voltage of 1.5 V
• Supports ECC and non-ECC, unbuffered DDR3 DIMMs
— Mixing of ECC and Non-ECC DIMMS is not supported
• Theoretical maximum memory bandwidth of:
— 17.1 GB/s in dual-channel mode assuming DDR3 1066 MT/s
— 21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Memory organizations:
— Single-channel modes
— Dual-channel modes - Intel
®
Flex Memory Technology:
Dual-channel symmetric (Interleaved)
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
•Intel
®
Fast Memory Access (Intel
®
FMA):
— Just-in-Time Command Scheduling
—Command Overlap
— Out-of-Order Scheduling
2.4.2 PCI Express*
The PCI Express* port(s) are fully-compliant to the PCI Express Base Specification,
Rev. 2.0.
The following configurations are supported:
Configuration 1
— One 16-lane PCI Express* port intended to connect Processor Root Port to PCH
End Point
— One 4-lane PCI Express* port intended for I/O
— Four single-lane PCI Express* ports intended for I/O via the PCH
Configuration 2
— One 8-lane PCI Express* port intended to connect Processor Root Port to PCH
End Point
— One 8-lane PCI Express* port intended for I/O
— One 4-lane PCI Express* port intended for I/O
— Four single-lane PCI Express* ports intended for I/O via the PCH
Configuration 3
— One 4-lane PCI Express* port intended to connect Processor Root Port to PCH
End Point
— Three 4-lane PCI Express* port intended for I/O