Datasheet

Processor Configuration Registers
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2 May 2012
158 Document Number: 327405
-001
11.8 ECCERRLOG1_C1 - ECC Error Log 1
B/D/F/Type: 0/0/0/MCHBAR MC1
Address Offset: 44CC-44CFh
Default Value: 00000000h
Access: ROS-V
Size: 32 bits
This register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the row and column address
information of the address block of main memory of which an error (single bit or multi-
bit error) has occurred.
11.9 MAD_DIMM_CH0 - Address Decode Channel 0
B/D/F/Type: 0/0/0/MCHBAR_MCMAIN
Address Offset: 5004-5007h
Default Value: 00600000h
Access: RW-L
1RO-P 0bPowergood
Multiple Bit Error Status (MERRSTS):
This bit is set when an uncorrectable multiple-bit error
occurs on a memory read data transfer. When this bit
is set, the address that caused the error and the error
syndrome are also logged and they are locked until
this bit is cleared.
This bit is cleared when the corresponding bit in
0.0.0.PCI.ERRSTS is cleared.
0RO-P 0bPowergood
Correctable Error Status (CERRSTS):
This bit is set when a correctable single-bit error
occurs on a memory read data transfer. When this bit
is set, the address that caused the error and the error
syndrome are also logged and they are locked to
further single bit errors, until this bit is cleared.
A multiple bit error that occurs after this bit is set will
override the address/error syndrome information.
This bit is cleared when the corresponding bit in
0.0.0.PCI.ERRSTS is cleared.
Table 11-9. Channel 1 ECC Error Log 0 (Sheet 2 of 2)
Bit Access
Default
Value
RST/
PWR
Description
Table 11-10.Channel 1 ECC Error Log 1
Bit Access
Default
Value
RST/
PWR
Description
31:16 ROS-V 0000h Powergood
Error Column (ERRCOL):
This field holds the DRAM column address of the
read transaction that had the ECC error.
15:0 ROS-V 0000h Powergood
Error Row (ERRROW):
This field holds the DRAM row (page) address of
the read transaction that had the ECC error.