Datasheet

Electrical Specifications
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012 Datasheet - Volume 1 of 2
Document Number: 327405
-001 113
Note: See Table 9-11 for TAP Signal Group DC specifications and Table 9-23 for TAP Signal Group AC
specifications.
Figure 9-8. PCI Express* Receiver Eye Margins
Figure 9-9. TAP Valid Delay Timing Waveform
Tx = T17: TDO Clock to Output Delay
Ts = T15: TDI, TMS Setup Time
Th = T16: TDI, TMS Hold Time
V = 0.5 * V
TT
TCK
Signal
Tx Ts Th
V Valid
V