Datasheet

Electrical Specifications

Intel

Xeon

and Intel

Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2 May 2012

112 Document Number: 327405

-001

Figure 9-6. DDR3 Receiver Eye Mask

Figure 9-7. DDR3 Clock to DQS Skew Timing Waveform

Vref + 100mV

Vref – 100mV

25%UI

5% UI

CK# (IMC)

DQS (IMC)

CK (IMC)

0.5 * V

DDQ

SKEW_CK-DQS