Datasheet
Intel
®
Xeon
®
Processor E7-8800/4800/2800 Product Families 25
Specification Update September 2012
Implication: Performance Monitoring Event WOKEN will under count the number of cores woken up
from core C-states due to Trusted Execution Technology transaction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BP35. PECI Command Average Temperature Read does not report correct
Temperature
Problem: The PECI (Platform Environment Control Interface) mailbox command 0x21, Average
Temperature Read, is a feature which calculates the average temperature of the
processor cores and reports it. In some instances the temperature reported out from
the PECI Command Average Temperature Read is significantly higher than the actual
processor average temperature.
Implication: The PECI Command Average Temperature Read may report a temperature that is
higher than the actual processor average temperature.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BP36. Intel
®
QPI Initialization May Cause a CATERR During Power-on Reset
Problem: In a complex set of circumstances during a power cycle reset, a CATERR may occur
during the Intel
®
QPI initialization sequence as a result of a race condition where a QPI
completion transaction arrives while the receiver is still going through its initialization.
Implication: One of the application processors PBSP (package BSP) may cause a CATERR assertion
resulting in a failure to complete BIOS post. This is only a boot issue and cannot occur
during run-time.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BP37. EOI Transaction May Not be Sent if Software Enters Core C6 During an
Interrupt Service Routine
Problem: If core C6 is entered after the start of an interrupt service routine but before a write to
the APIC EOI (End of Interrupt) register, and the core is woken up by an event other
than a fixed interrupt source the core may drop the EOI transaction the next time APIC
EOI register is written and further interrupts from the same or lower priority level will
be blocked.
Implication: EOI transactions may be lost and interrupts may be blocked when core C6 is used
during interrupt service routines.
Workaround: Software should check the ISR register and if any interrupts are in service only enter
C1.
Status: For the steppings affected, see the Summary Tables of Changes.
BP38. A First Level Data Cache Parity Error May Result in Unexpected
Behavior
Problem: When a load occurs to a first level data cache line resulting in a parity error in close
proximity to other software accesses to the same cache line and other locked accesses
the processor may exhibit unexpected behavior.
Implication: Due to this erratum unpredictable system behavior may occur. Intel has not observed
this erratum with any commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.