Datasheet
Intel
®
Xeon
®
Processor E7-8800/4800/2800 Product Families 23
Specification Update September 2012
BP26. Task Switch to a TSS With an Inaccessible LDTR Descriptor May Cause
Unexpected Faults
Problem: A task switch may load the LDTR (Local Descriptor Table Register) with an incorrect
segment descriptor if the LDT (Local Descriptor Table) segment selector in the new TSS
specifies an inaccessible location in the GDT (Global Descriptor Table).
Implication: Future accesses to the LDT may result in unpredictable system behavior.
Workaround: Operating system code should ensure that segment selectors used during task switches
to the GDT specify offsets within the limit of the GDT and that the GDT is fully paged
into memory.
Status: For the steppings affected, see the Summary Tables of Changes.
BP27. An Intel
®
QPI Link Layer Retry Quickly Followed by an Intel
®
QPI
Physical Layer Reset May Cause an MCE
Problem: While an Intel
®
QPI link is processing a link level retry requested by a remote
Intel
®
QPI agent (due to link CRC errors), if an Intel
®
QPI phy layer reset is triggered
and aligns with a specific retry stage, a packet may get dropped and cause time out
error with MCA error code, IA32_MCi_Status [15:0] encoded as a Bus and Interconnect
Error with Timeout [bit 8] = 1, Cache Hierarchy Error, or Internal Timer error.
Implication: Due to this erratum, a fatal MCE may be signaled with MCA error code,
IA32_MCi_Status [15:0] encoded as a Bus and Interconnect Error with Timeout [bit 8]
= 1, Cache Hierarchy Error, or Internal Timer error.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BP28. LLC Arrays May have Incorrect Values after Warm Reset when Memory
BIST is Disabled
Problem: When Memory BIST is disabled in the platform, LLC (Last Level Cache) arrays do not
get initialized properly when coming out of warm reset.
Implication: Due to this erratum, data may be left valid in the LLC array which subsequently may be
used/consumed by the processor during BIOS execution leading to unpredictable
system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BP29. VM Entries that Return from SMM May Incorrectly Write to the SMRR
Protected Region
Problem: If the executive-VMCS pointer field in the VMCS does not contain the VMXON pointer
and the “use TPR shadow” VM-execution control is 1 in the executive VMCS, a VM entry
that returns from SMM may write to the virtual-APIC page. Due to this erratum, this
write may occur even if the virtual-APIC page is in the region protected by the SMRR
(system-management range register).
Implication: The writes to the virtual-APIC page may corrupt data in SMRAM.
Workaround: If software sets the “use TPR shadow” VM-execution control to 1, it should not
VMWRITE the virtual-APIC address to an address in the range protected by the SMRR.
Status: For the steppings affected, see the Summary Tables of Changes.
BP30. System Quiesce Events Initiated While Power Events are In Progress
May Cause System Hangs
Problem: BIOS initiation of a system quiesce flow via the QUIESCE_CONTROL2 MSR (51H) and
exit of a system quiesce flow QUIESCE_CONTROL1 MSR (50H) via may conflict with a
power event on the BSP (Boot Strap Processor) core. Due to this conflict, the BSP core,